Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure.
Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at the forefront of Smart, Secure Everything with the world’s most advanced tools for silicon chip design, verification, IP integration, and application security testing. Our technology helps customers innovate from Silicon to Software, so they can deliver Smart, Secure Everything.
Synopsys’ Security IP solutions include a range of cryptography cores, security protocol accelerators and processors, embedded security IP modules, secure boot and cryptography middleware as well as content protection IP for integration into system-on-chips. These integrated solutions enable the most efficient silicon design and highest level of security to help prevent a wide range of evolving threats in connected devices such as theft, tampering, side channels attacks, malware and data breaches.
Starting Fall 2020, this 8- or 12-month internship will be with our Solutions Group in our Nepean office.
We are seeking a highly motivated and innovative digital verification engineering intern with strong theoretical and practical background in high-speed data recovery circuits. You will be working as part of a highly experienced mixed-signal design team and you will be involved in verifying current and next generation Backplane Ethernet, PCIe, SATA, and USB 2/3 SERDES products. The position offers an excellent opportunity to work with an expert team of digital and mixed signal engineers responsible for delivering high-end mixed-signal designs.
What you will do:
Writing constrained-random SystemVerilog testbenches using UVM and VMM;
Creating and analyzing functional coverage and assertion coverage, and analyzing code coverage;
Defining and tracking verification testplans;
Debugging RTL and gate-level simulation failures;
SystemVerilog analog behavior modelling;
Experience writing scripts in languages such as Perl and Unix shell
Familiar with Verilog and SystemVerilog.
Enrolled in a Master or PhD program in Computer Engineering or Electrical Engineering, or similar
Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact email@example.com.